use crate::ddma::regs::*;
use crate::ddma::types::Ddma;

impl Ddma {
    pub fn enable(&self) {
        unsafe {
            write_reg32(self.base(), FDDMA_CTL, FDDMA_CTL_ENABLE);
        }
    }

    pub fn reset(&self) {
        unsafe {
            write_reg32(self.base(), FDDMA_CTL, FDDMA_CTL_SRST);
            write_reg32(self.base(), FDDMA_CTL, 0);
        }
    }

    pub fn configure_chan_basic(&self, ch: usize, dev_addr: u32, ddr_addr: u64, bytes: u32, rx_mode: bool) {
        unsafe {
            // DDR address high/low
            write_reg32(self.base(), FDDMA_CHAN_DDR_UP_ADDR(ch), (ddr_addr >> 32) as u32);
            write_reg32(self.base(), FDDMA_CHAN_DDR_LOW_ADDR(ch), (ddr_addr & 0xffff_ffff) as u32);
            write_reg32(self.base(), FDDMA_CHAN_DEV_ADDR(ch), dev_addr);
            write_reg32(self.base(), FDDMA_CHAN_TS(ch), bytes);
            // CTRL: EN | DIR
            let mut ctrl = 0u32;
            if rx_mode { ctrl |= 1 << 2; }
            ctrl |= 1; // EN
            write_reg32(self.base(), FDDMA_CHAN_CTRL(ch), ctrl);
        }
    }
}


